Third-party components in this directory (the NEORV32 demo of the FPGA Project Analyzer)
=======================================================================================

* neorv32_sim.wasm / neorv32_sim.js: NEORV32 v1.13.7 RTL (BSD-3-Clause, license below),
  converted by GHDL and Verilator; it includes the Verilator runtime (LGPL-3.0-only or
  Artistic-2.0, https://verilator.org) and the Emscripten runtime and libc (MIT / NCSA,
  https://github.com/emscripten-core/emscripten). The boot ROM image inside it is the NEORV32
  bootloader shipped with the RTL.
* programs/*.bin: NEORV32 v1.13.7 example programs and software library (BSD-3-Clause,
  license below). game_of_life_64x20 is upstream game_of_life with a smaller universe.
* programs/benchmark.bin: derived from EEMBC CoreMark (https://github.com/eembc/coremark) with the
  NEORV32 port (https://github.com/stnolting/neorv32-coremark), Apache-2.0
  (http://www.apache.org/licenses/LICENSE-2.0). Modified: 1 iteration, minimal printf, no float,
  static memory, no 10-second runtime rule, renamed output; sized for 16 KiB IMEM. Its results
  are not CoreMark scores. CoreMark is a trademark of EEMBC.
* design.html: generated by the FPGA Project Analyzer (MIT); it embeds elkjs (EPL-2.0,
  https://github.com/kieler/elkjs).

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