FPGA Project Analyzer (fpa)

See and review Vivado, Zynq and PYNQ projects visually: drill-down Vivado-style diagrams, plus the bugs that "timing met" hides. A CLI and an AI agent skill.

Live demo: NEORV32 RISC-V SoC fpa's diagram of the unmodified NEORV32 v1.13.7 RTL next to the same RTL simulated live in your browser (GHDL, Verilator, WebAssembly). Load programs through the real bootloader and watch the blocks light up. Source, install and usage on GitHub github.com/al-nafisah/fpga-project-analyzer