NEORV32 RISC-V SoC: diagram and live RTL simulation

Left: the FPGA Project Analyzer (fpa) diagram of unmodified NEORV32 v1.13.7 RTL (neorv32_test_setup_bootloader with the Arty A7 constraints). Right: the same RTL running live in your browser, converted GHDL → Verilog → Verilator → WebAssembly and clocked at a real-time 1 MHz. Blocks glow while the simulated SoC uses them; click a glowing block to jump to its widget, double-click to open it.

active in the simulation in the RTL but not enabled in this configuration
loading the simulator…
 

UART0 terminal

19200 8N1. Click and type: keys go to the UART as raw bytes (bootloader commands are single keys, no Enter).

GPIO LEDs

gpio_o[7:0]. The bootloader blinks LED 0.

Programs

Click one to reset the SoC and upload it through the bootloader.

    Activity

    Requests per cycle for each block (the same numbers drive the glow).